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Technology independent VLSI-Design using Bit Level self-timed circuits

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2 Author(s)
C. Heer ; Abteilung für Allgemeine Elektrotechnik und Mikroelektronik, Universität Ulm, Oberer Eselsberg, D-7900 Ulm ; O. Aumann

In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5μm-and a 0,8μm-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5μm) up to 100 MHz (0,8μm) have been measured for self-timed asynchronous test circuits.

Published in:

Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European

Date of Conference:

21-23 Sept. 1992