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Race-Free Clocking of CMOS Pipelines through a Single Global Clock

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2 Author(s)
C. H. Lau ; Department of Electrical Engineering, University of Edinburgh, King's Buildings, Edinburgh EH9 3JL ; D. Renshaw

To ease global clock distribution in a synchronous system extending over several levels of interconnect (for example between logic blocks within a chip, chips mounted on a printed circuit board and boards of chips across a backplane), a race-free clocking scheme for CMOS VLSI requiring a single clock line is presented. Since the technique is race-free, the clock line may be driven by a sinusoid, thereby avoiding the transmission of the higher frequency components associated with fast clock edges. In this way, clock signal distortion due to transmission line effects will be kept to a minimum.

Published in:

Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European

Date of Conference:

20-22 Sept. 1989