Power Dissipation Analysis of CMOS VLSI Circuits by means of Switch-Level Simulation

A method has been defined to analyze the power dissipation of CMOS VLSI circuits by means of switch-level simulation. Random vectors are used as stimuli to the circuit to ensure vector-independentness. The method has been implemented using an existing mixed-level simulator. Results are described for a range of circuits, including a 20,000 transistor one.