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A high speed Analog-Digital converter realized with a standard Bipolar process (Ft = 8 GHz) is presented. Optimized design and novel layout concept of the chip, leads to operating frequency up to 1 GHz sampling rate with less than 1.4 W power dissipation. The architecture and the design of the main functions are described. The way to optimize dynamic performance is shown in the paper. Main measurement results are : Differential Non linearity of ± 0.15 LSB, analog input bandwidth of 550 MHz, Nyquist operation up to 500 MHz sampling rate.
Published in:
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
(Volume:1
)
Date of Conference: 19-21 Sept. 1990
- Page(s):
- 81 - 84
- Print ISBN:
- 2-86332-087-4
- INSPEC Accession Number:
- 12404502
- Conference Location :
- Grenoble
- Product Type:
- Conference Publications
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