By Topic

AGOSTO: A Framework to Generate Weighted Random Patterns for VLSI Built-In Self-Test

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Miranda, Miguel A. ; Departamento de Ingenier?a Electr?nica, E.T.S.I. Telecommunicaci?n, Universidad Polit?cnica de Madrid, Ciudad Universitaria s/n. 28040 Madrid. Spain. phone: +34.1.3367322, fax: +34.1.3367323, email: ; Santos, Andres ; Nieto-Taladriz, Octavio

A new probabilistic approach to find optimized distributions of weights for VLSI Built-In Self-Test is presented. Most of previous approaches are based on the use of multiple distributions of weights to obtain significant reduction of test length. However, those approaches consume large memory areas to store the different distributions. The presented generation scheme improves the are efficiency by generating only one distribution of weights highly optimized, so that, the memory area overhead is reduced considerably.

Published in:

Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European  (Volume:1 )

Date of Conference:

22-24 Sept. 1993