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A new probabilistic approach to find optimized distributions of weights for VLSI Built-In Self-Test is presented. Most of previous approaches are based on the use of multiple distributions of weights to obtain significant reduction of test length. However, those approaches consume large memory areas to store the different distributions. The presented generation scheme improves the are efficiency by generating only one distribution of weights highly optimized, so that, the memory area overhead is reduced considerably.
Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European (Volume:1 )
Date of Conference: 22-24 Sept. 1993