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A Pipelined Digital Filter Chip with a Throughput Rate of 100 Mbit/s

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2 Author(s)

A digital lowpass filter for an image coding and processing system is described. To achieve the high throughput rate (up to 100 Mbit/s) a pipeline-organization had to be used. The mapping of the filter function to a regular pipeline configuration in bit-slice technique is explained. The circuit was implemented in a standard 2 ¿m NMOS-technique. The 3.2×1.7 mm2 chip needs 3500 transistors and consumes 250 mW.

Published in:

Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European

Date of Conference:

0-0 Sept. 1984