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Key Circuit Techniques for a High-Speed, Low-Power Psram using the BICMOSG3 Cell for Storage Array

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5 Author(s)
Matzke, W.-E. ; Inst. for Phys. of Semicond., Frankfurt (Oder), Germany ; Winkler, W. ; Richter, R. ; Perbandt, A.
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This paper describes the architecture and key circuit techniques of a PSRAM using the BiCMOSG3 cell for storage array. The important features of the cell from the circuit techniques point of view are reported. An inverting refresh scheme resulting in a very simple refresh circuitry is proposed. The functional separation between refresh amplifiers and sense amplifiers for selective access operations permits very fast access operations. A 16-kbit test memory was designed as a part of a 1-Mbit PSRAM concept. The delay time in the storage array is 4 ns.

Published in:

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European  (Volume:1 )

Date of Conference:

19-21 Sept. 1990