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Time-Predictable Out-of-Order Execution for Hard Real-Time Systems

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2 Author(s)
Whitham, Jack ; Dept. of Comput. Sci., Univ. of York, York, UK ; Audsley, N.

Superscalar out-of-order CPU designs can achieve higher performance than simpler in-order designs through exploitation of instruction-level parallelism in software. However, these CPU designs are often considered to be unsuitable for hard real-time systems because of the difficulty of guaranteeing the worst-case execution time (WCET) of software. This paper proposes and evaluates modifications for a superscalar out-of-order CPU core to allow instruction-level parallelism to be exploited without sacrificing time predictability and support for WCET analysis. Experiments using the M5 O3 CPU simulator show that WCETs can be two-four times smaller than those obtained using an idealized in-order CPU design, as instruction-level parallelism is exploited without compromising timing safety.

Published in:

Computers, IEEE Transactions on  (Volume:59 ,  Issue: 9 )

Date of Publication:

Sept. 2010

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