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Effect of Floating-Gate Polysilicon Depletion on the Erase Efficiency of nand Flash Memories

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6 Author(s)
Alessio Spessot ; R&D¿Technology Development, Numonyx, Agrate Brianza, Italy ; Christian Monzio Compagnoni ; Fabrizio Farina ; Alessandro Calderoni
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This letter presents a detailed experimental investigation of the erase transients of decananometer NAND Flash memories, showing a drop and then a recovery of the erase efficiency as the erase bias is increased. The modulation of the erase efficiency is studied as a function of the erase time, temperature, and the number of applied pulses: Longer erase times or higher temperatures are shown to reduce the efficiency drop, while this is enhanced when the erase pulse is split into a sequence of short pulses. Experimental evidences are explained as a result of the deep-depletion condition that exists in the floating-gate polysilicon for moderate erase biases and short erase times, reducing the electric field in the tunnel oxide and the electron-tunneling current discharging the floating gate.

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IEEE Electron Device Letters  (Volume:31 ,  Issue: 7 )