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SyncLink: high-speed DRAM for the future

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1 Author(s)
Diamond, S.L. ; Picosoft Inc., San Mateo, CA, USA

In 1987 it was becoming apparent that computer systems would need to communicate at data rates beyond the capabilities of then current approaches. To take on this challenge, the IEEE Futurebus group formed a new group dedicated to building a fast, coherent interface, scalable from the smallest computer to the largest mainframe. The IEEE officially established the SCI (Scalable Coherent Interface) working group, referenced as IEEE P1596, in 1988. Today the SCI is IEEE Std 1596. It has several derivatives that enhance its operation and meet additional needs such as real-time operations: a differential voltage specification (IEEE 1536.3), a point-to-point memory interface (IEEE 1596.4), and SyncLink (IEEE P1596.7). SyncLink is a new, high-speed memory interface that combines synchronous dynamic RAM (SDRAM), developed in the late 1980s, and the IEEE's RamLink interface, developed in 1990. SyncLink uses the earlier interface's packet protocol as a base but eliminates its point-to-point link to reduce latency. The new interface uses SDRAM's internal pipelining and control for efficient bus utilization. It allows access in the lowest latency possible for a very high bandwidth DRAM. Future plans include data rates of 800 Mbits per pin per second in 1998, to double in the early 2000s. This rate will allow systems to operate at full capability, even when running 3D graphics

Published in:

Micro, IEEE  (Volume:16 ,  Issue: 6 )