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Architectural design exploration of chip-scale photonic interconnection networks using physical-layer analysis

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4 Author(s)
Chan, J. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Hendry, G. ; Biberman, A. ; Bergman, K.

We conduct an architectural exploration of three chip-scale photonic interconnection networks in a novel simulation environment, exploring insertion loss, crosstalk, and energy. The impact of these metrics is evaluated in the context of network performance.

Published in:
Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC)

Date of Conference: 21-25 March 2010

Page(s):
1 - 3
E-ISBN :
978-1-55752-884-1
INSPEC Accession Number:
11306608
Conference Location :
San Diego, CA
Product Type:
Conference Publications

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