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Instruction scheduling for a superscalar architecture

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2 Author(s)
Collins, R. ; Hertfordshire Univ., Hatfield, UK ; Steven, G.B.

It is increasingly accepted that superscalar processors can only achieve their full performance potential through compile-time instruction scheduling. The paper presents preliminary performance results using a conditional group scheduler which targets the HSA processor model developed at the University of Hertfordshire. In particular, we show that guarded instruction execution improves performance by allowing the processor to squash instructions in the instruction buffer before they are issued to functional units and enables the scheduler to delete a significant number of branch instructions

Published in:

EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

Date of Conference:

2-5 Sep 1996