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A FPGA based square-root coprocessor

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3 Author(s)
Tchoumatchenko, V. ; Dept. of Electron., Tech. Univ. Sofia, Bulgaria ; Vassileva, T. ; Gurov, P.

We present an FPGA implementation of a non-restoring integer square-root algorithm, that uses estimates for result-digit selection and radix-2 redundant addition in recurrence. On-the-fly conversion of the result-digit and signed-digit adder/substractor are used to simplify the hardware realization. Modifications of the equations for th optimal use of Xilinx CLBs, and the necessary CLB resources for different bit-length calculations are outlined, for the XC3000 family

Published in:

EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

Date of Conference:

2-5 Sep 1996