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Standard processors have logical resources necessary for implementing various calculating platforms, capable to execute applications in different fields such as communication, command and control or signal processing. However, the sequential aspect of executing the instructions, the speed limit given by the access to the memory block and the standard architecture of the processors, dictate some of the systems limitations regarding its performance. A solution that can increase the performance for a specified application, is the hardware implementation of the calculating platform using the Field Programmable Gate Array. This paper presents a principle on how performance can be improved in the context of Microcontroller Units applications, using the Instruction Set Architecture of a conventional Reduced Instruction Set Computer, over Field Programmable Gate Array. It concludes how this idea could be suggested as a principle at a higher scale, in designing dedicated System-On-Chip with the Field Programmable Gate Array.