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Prediction of Electromigration Induced Voids and Time to Failure for Solder Joint of a Wafer Level Chip Scale Package

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3 Author(s)
Yong Liu ; Fairchild Semicond. Corp., South Portland, ME, USA ; Yuanxing Zhang ; Lihua Liang

This paper proposes a new prediction method for electromigration (EM) induced void generation of solder bumps in a wafer level chip scale package. The methodology is developed based on discretized weighted residual method in a user-defined finite element analysis framework to solve the local ME governing equation with the variable of atomic concentration. The local solution of atomic concentration is incorporated in the multiphysics environment for electrical, thermal and stress in both sub-model and global model. The new method takes the advantage of solving the variable of atomic density, it avoids directly solving the divergences of the atomic flux, which includes the atomic density gradient items and is very hard and challenging to get the solution by traditional method. Comparison of the atomic density distributions with and without considering the atomic density gradient for representive nodes is investigated. The simulation results for voids and time to failure (TTF) are discussed and correlated with previous test results. Finally, the analysis of the impact of under ball metallurgy and solder bump geometry on the void generation and TTF is presented.

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Components and Packaging Technologies, IEEE Transactions on  (Volume:33 ,  Issue: 3 )