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This letter presents an approach to automatically synthesize embedded software. Starting from an instruction set architecture description of a hardware platform and a formal specification of the input-output behavior of a program to be realized, a control sequence of minimal length is generated. The proposed approach uses formal techniques, i.e., the synthesis problem is mapped to an instance of satisfiability of quantified Boolean formulas. We give experimental results and discuss the advantages, as well as future challenges of the proposed approach.
Date of Publication: Sept. 2010