By Topic

Beta Distribution Based Slew Evaluation Approach for On-Chip RC Interconnects by Using Moment Matching Technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Kar, R. ; Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Durgapur, India ; Maheshwari, V. ; Pathak, S. ; Reddy, M.S.K.
more authors

With the development of technology, as it is scaling towards nanometer regime, for optimizations like physical synthesis and static timing analysis, accurate interconnect delay and slew computation has become critical. The timing verification of digital integrated circuits has become an extremely difficult task due to statistical variations in the gate and wire delays. Statistical timing analysis techniques are being developed to tackle this important problem. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. So efficient interconnect delay and slew computation has become critical in this era. Slew rate determines the ability of a device to handle the varying signals. Determination of slew rate to a good proximity is very much essential for efficient design of high speed CMOS integrated circuits. This work presents an accurate and efficient model to compute the slew metric of on-chip interconnect of high speed CMOS circuits. Our slew metric assumption is based on the Beta Distribution function. The Beta distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model, the stability of the Beta Distribution model is guaranteed.

Published in:

Recent Trends in Information, Telecommunication and Computing (ITC), 2010 International Conference on

Date of Conference:

12-13 March 2010