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A 12-b, 10-MHz, 250-mW CMOS A/D converter

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5 Author(s)
Gil-Cho Ahn ; Dept. of Electr. Eng., Sogang Univ., Seoul, South Korea ; Hee-Cheol Choi ; Shin-Il Lim ; Seung-Hoon Lee
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A 12-b, 10-MHz, 250-mW, four-stage analog-to-digital converter (ADC) was implemented using a 0.8-μm p-well CMOS technology. The ADC based on a digitally calibrated multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted capacitor array in the front-end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield. All the analog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm2 (4.2 mm×3.6 mm). Measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype are less than ±0.8 LSB and ±1.8 LSB, respectively

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 12 )