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A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links

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2 Author(s)
Yang, C.-K.K. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Horowitz, M.A.

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-μm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3× oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3×3 mm2

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 12 )

Date of Publication:

Dec 1996

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