Skip to Main Content
Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-??m triple-well common-source complementary metal-oxide-semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 ??.