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Low-power L2 cache design for multi-core processors

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2 Author(s)
Chung, C.-M. ; Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., Seoul, South Korea ; Kim, J.

A low-power set-associative L2 cache design for a multi-core processor is proposed. Since this way-predicting L2 cache (WP-L2) predicts a destination way and accesses only the predicted way, it consumes less energy than a conventional set-associative L2 cache. Exploiting access patterns of an L2 cache, WP-L2 is based on two prediction logics; a look-ahead buffer (LAB) predicts the next sequential cache block and a way-affinity table (WAT) records the way number of the previous L2 cache access. Combining the logics, WP-L2 predicts correct ways for about 83% of L2 cache accesses and reduces about 22% of access latency and 44% of energy consumption compared to the conventional eight-way set-associative L2 cache.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 9 )