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A fully-asynchronous low-power framework for GALS NoC integration

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3 Author(s)
Thonnart, Y. ; CEA-LETI, MINATEC, Grenoble, France ; Vivet, P. ; Clermidy, F.

Requiring more bandwidth at reasonable power consumption, new communication infrastructures must provide adequate solutions to guarantee performance during physical integration. In this paper, we propose the design of a low-power asynchronous Network-on-Chip which is implemented in a bottom-up approach using optimized hard-macros. This architecture is fully testable and a new design flow is proposed to overcome CAD tools limitations regarding asynchronous logic. The proposed architecture has been successfully implemented in CMOS 65nm in a complete circuit. It achieves a 550Mflit/s throughput on silicon, and exhibits 86% power reduction compared to an equivalent synchronous NoC version.

Published in:

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Date of Conference:

8-12 March 2010