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An integrated framework for joint design space exploration of microarchitecture and circuits

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5 Author(s)
Azizi, O. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Mahesri, A. ; Stevenson, J.P. ; Patel, S.J.
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The design of a digital system for energy efficiency often requires the analysis of circuit tradeoffs in addition to architectural tradeoffs. To assist with this analysis, we present a framework for performing joint exploration of both the architectural and circuit design spaces. In our approach, we use statistical inference techniques to create a model of a large micro-architectural design space from a small number of simulation samples. We then characterize the design tradeoffs of each of the underlying circuits and integrate these with the higher level architectural models to define the joint circuit-architecture design space. We use posynomial forms for all our models, enabling the use of convex optimization tools to efficiently search the joint design space. As an example, we apply this methodology to explore the power-performance tradeoffs in a dual-issue superscalar out-of-order processor, showing how the framework can be used to determine the optimal set of design parameters for energy efficiency. Compared to current architectural tools that use fixed circuit costs, joint optimization can reduce energy by up to 30% by considering circuit tradeoff characteristics.

Published in:

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Date of Conference:

8-12 March 2010

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