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On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits

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4 Author(s)
Weerasekera, R. ; Centre for Microsyst. Eng., Lancaster Univ., Lancaster, UK ; Grange, M. ; Pamunuwa, D. ; Tenhunen, H.

This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.

Published in:

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Date of Conference:

8-12 March 2010