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Computation of yield-optimized Pareto fronts for analog integrated circuit specifications

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2 Author(s)
Mueller-Gritschneder, D. ; Inst. for Electron. Design Autom., Tech. Univ. Muenchen, Munich, Germany ; Graeb, H.

For any analog integrated circuit, a simultaneous analysis of the performance trade-offs and impact of variability can be conducted by computing the Pareto front of the realizable specifications. The resulting Specification Pareto front shows the most ambitious specification combinations for a given minimum parametric yield. Recent Pareto optimization approaches compute a so-called yield-aware specification Pareto front by applying a two-step approach. First, the Pareto front is calculated for nominal conditions. Then, a subsequent analysis of the impact of variability is conducted. In the first part of this work, it is shown that such a two-step approach fails to generate the most ambitious realizable specification bounds for mismatch-sensitive performances. In the second part of this work, a novel single-step approach to compute yield-optimized specification Pareto fronts is presented. Its optimization objectives are the realizable specification bounds themselves. Experimental results show that for mismatch-sensitive performances the resulting yield-optimized specification Pareto front is superior to the yield-aware specification Pareto front.

Published in:

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Date of Conference:

8-12 March 2010