By Topic

Post-layout optimization for deep submicron design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Sato, K. ; Advanced CAD Dev. Lab., NEC Corp., Kawasaki, Japan ; Kawarabayashi, M. ; Emura, H. ; Maeda, N.

To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buffers based on back-annotated detailed routing information. During optimization, inserted buffers are assumed to be placed on the appropriate location of original wires so as to calculate accurate wire RC delay. With forward annotated location information of inserted buffers, the layout system attempts to preserve patterns of original wires using the ECO technique. Our experimental results show that this technique combined with the conventional gate sizing technique achieves up to 41.2% delay reduction after the initial layout

Published in:

Design Automation Conference Proceedings 1996, 33rd

Date of Conference:

3-7 Jun, 1996