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Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

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4 Author(s)
Lee, M.T.-C. ; Fujitsu Labs. of America, Santa Clara, CA, USA ; Yu-Chin Hsu ; Ben Chen ; Fujita, M.

This paper presents our experience on domain-specific high-level modeling and synthesis for Fujitsu ATM switch design. We propose a high-level design methodology using VHDL, where ATM switch architectural features are considered during behavior modeling, and a high-level synthesis compiler, MEBS, is prototyped to synthesize the behavior model down to a gate-level implementation. Since the specific ATM switch architecture is incorporated into both modeling and syntheses phases, a high-quality design is efficiently derived. The synthesis results show that given the design constraints, the proposed high-level design methodology can produce a gate-level implementation by MEBS with about 15% area reduction in shorter design cycle when compared with manual design

Published in:

Design Automation Conference Proceedings 1996, 33rd

Date of Conference:

3-7 Jun, 1996

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