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A Multi-DSP Based Low-Latency Video Processing System

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4 Author(s)
Dandan Lei ; Digital Media Lab., BUAA, Beijing, China ; Hongxu Jiang ; Bo Li ; Xiaonan Ji

In this paper, a multi-DSP based low-latency video processing system is designed, in which one TMS320C6455 and one TMS320DM642 produced by TI are used as kernel processors. Several functions have been implemented, such as video deinterlacing and H.264 encoding. Not only could it have more uniform image quality, but also it greatly reduces the system latency. Considering the VLIW architecture and the memory resource limitation of TMS320C6000 DSPs, the paper optimizes the data storage and transfer respectively in order to reduce the processing latency and enhance the system's performance; Moreover, by analysing the existing video-coding algorithm, a low latency video-coding algorithm structure is put forward to improve the inherent latency.

Published in:

2009 First International Conference on Information Science and Engineering

Date of Conference:

26-28 Dec. 2009