By Topic

Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator for System-on-Chips

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chenchang Zhan ; Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China ; Wing-Hung Ki

A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ??m CMOS technology ( Vtn ?? 0.52 V and Vtp ?? -0.72 V). The output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ??A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 5 )