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A versatile frequency synthesizer for a L1/L5 dual-band GPS/Galilleo dual-mode RF receiver is designed with a 0.13 ??m CMOS process. For spur reduction, a simple low-glitch charge-pump circuit (CPC) is proposed in this letter. The fabricated chip achieves the in-band phase noise of -92 dBc/Hz and the spur performance of -71.23 dBc at 8.184 MHz offset from 1.571 GHz carrier with a second-order loop filter.
Date of Publication: June 2010