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CORDIC implementation with parameterizable ASIC/SoC flow

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4 Author(s)
Zhenyu Qi ; Charles L. Brown ECE Dept., Univ. of Virginia, Charlottesville, VA, USA ; Cabe, A.C. ; Jones, R.T. ; Stan, M.R.

A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350 nm and 65 nm, using a script-based, parameterizable ASIC/SoC flow that can be easily adapted for different designs and technologies for fast concept-to-silicon mapping. Power numbers at both technology nodes are reported for the CORDIC design. The contribution of the paper includes both the actual design and the design flow.

Published in:

IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the

Date of Conference:

18-21 March 2010