Skip to Main Content
Side-channel attacks have become a threat to secure electronic circuits, due to the strong correlation between data pattern and leaking power/timing information. By monitoring the power/timing behavior of a synchronous circuit, an attacker can easily obtain the secret data stored in the device. Although dual-rail asynchronous circuits have more stable power traces, they still show power fluctuation because of the imbalanced load between two rails. Moreover, asynchronous circuits are the most prone to timing attacks since delay is data dependent. Dual-spacer Dual-rail Delay-insensitive Logic (D3L), presented in this paper, is able to mitigate power and timing based side-channel attacks. Power fluctuation is decoupled from data pattern by the use of a dual-spacer protocol, while timing-data correlation is broken by insertion of random delays.