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Low-Power and High-Performance Communication Mechanism for Dependable Embedded Systems

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6 Author(s)
Hanawa, T. ; Center for Comput. Sci., Univ. of Tsukuba, Tsukuba, Japan ; Boku, T. ; Miura, S. ; Okamoto, T.
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Recently, a multi-core processor has been used to improve the performance and to reduce the power consumption. In order to acquire higher performance, multiprocessor connected with the network can enlarge the processing power. Dependability is also important for the embedded system to protect from a fault and failure. We develop a parallel platform for dependable embedded system, and investigate the low-power, reliable, and high-performance communication mechanism for such platform. In this study, we propose a communicator with communication links using PCI Express Gen2, and it denotes that maximum bandwidth is 2GB/s and several watts is required for power consumption. Moreover, this platform provides fault tolerance using redundancy.

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), 2008 International Workshop on

Date of Conference:

21-23 Jan. 2008