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Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators

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9 Author(s)
Takahashi, C. ; Univ. of Tsukuba, Tsukuba, Japan ; Sato, M. ; Takahashi, D. ; Boku, T.
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In this paper, we design an on-chip memory processor with arithmetic accelerators, which are expected to improve power consumption. In addition, we evaluate the power performance of the processor. We propose implementing vector-type arithmetic accelerators and SIMD-type arithmetic accelerators in the on-chip memory processor. The evaluation results obtained using our simulator indicate that the performance of the 4FMAs SIMD-type accelerators is similar to that of the 4FMAs vector-type accelerators on DAXPY, Livermore kernel 1 and 3. However, the performance of the 4FMAs vector-type accelerator exceeds that of the 4FMAs SIMD-type accelerator with respect to matrix multiplication and QCD because of difference in element size of the registers. On Livermore kernel 7, the power performance of the 4FMAs SIMD-type accelerators exceeds that of the 4FMAs vector-type because of register reuse. However, the 16FMAs vector-type accelerators have an advantage in almost all simulations, excluding main memory bandwidth intensive benchmarks.

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), 2008 International Workshop on

Date of Conference:

21-23 Jan. 2008