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A PLD Architecture for High Performance Computing

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5 Author(s)
Hirakawa, N. ; Graduated Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan ; Yoshihara, M. ; Tanigawa, K. ; Hironaka, T.
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In recent years, Field Programmable Gate Arrays (FPGAs) have been used for High Performance Computing (HPC). Because there is a significantly difference between configuration speed of FPGA and execution speed of Central Processing Unit (CPU), the difference causes performance degradation. To resolve of this problem, we proposed MPLD as a new Programmable Logic Device (PLD) architecture with high speed reconfiguration. The merits of the MPLD in HPC are high speed configuration and easy partial configuration.This is achieved by the configuration method which is same as write memory access of conventional parallel memory. In this paper, we describe the problems of FPGA on using it in HPC, and present the MPLD architecture which solves the problems. Some evaluation results of the prototype MPLD chip which implemented by using five metal layers ROHM 0.18¿m CMOS technology are also presented. As results, memory capacity of the prototype MPLD was 49152bit, and the core area was 1767.54 × 1690.96¿m2 and the number of metal layers used for wiring was three. The achieved configuration time is about 6.6¿sec for whole prototype MPLD. The configuration speed of the prototype MPLD is about 11.7 times higher than AS configuration used for Altera FPGAs.

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), 2008 International Workshop on

Date of Conference:

21-23 Jan. 2008