Skip to Main Content
Multi-level modulation of a 16.8-GHz class-E power amplifier with negative resistance enhanced power gain is demonstrated in a 130-nm CMOS process. The circuit achieves power gain of ~ 30 dB, and power-added efficiency (PAE) of 16% for the highest output power level of 6.8 dBm. The average efficiency for a random data pattern is ~ 8%. The circuit also exhibits 10-dBm saturated output power and ~ 22% maximum PAE. By realigning the highest output power level to the 10-dBm saturated output power, the efficiency can be improved. For a random data pattern, this PA should achieve ~ 2X higher efficiency than Class A PAs. The circuit supports seven amplitude levels for 400 Megabits per second (Mbps) data transmission. The multi-level output signal levels follow a square-root relation. The circuit including an address decoder occupies ~ 1.4 mm2.