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An architectural solution for designing and implementing low THD oscillators is presented. A digital harmonic-cancellation-block is used to suppress the low-frequency harmonics while a passive, inherently linear, filter is used to suppress the high-frequency ones. The proposed technique eliminates the need for typical high-Q BPF to suppress the harmonics. Thus, eradicates the effect of increasing device nonlinearities in the nanometric technologies by having pure digital solution. In addition, eliminating the need for high-Q band-pass-filter (BPF) releases the output swing from the constraints imposed by the linearity of the filter. The prototype is fabricated in 0.13 Â¿m CMOS technology. Measurement results show -72 dB THD at 10 MHz along with a differential output swing of 228 mVpp. The oscillator prototype can be tuned from 5 MHz to 11 MHz with less than 4.5 dB variations in the THD. The circuit consumes 3.37 mA from 1.2 V supply at 10 MHz and occupies an area of 0.186 mm2. As the performance depends solely on the timing precision of digital signals, the proposed oscillator is considered the best time-mode-based oscillator in literature.
Date of Publication: May 2010