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A 10-bit Charge-Redistribution ADC Consuming 1.9 
W at 1 MS/s
A 10-bit Charge-Redistribution ADC Consuming 1.9
This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115Ã225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:45
,
Issue:
5
)
Date of Publication: May 2010
- Page(s):
- 1007 - 1015
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11260133
- Digital Object Identifier :
- 10.1109/JSSC.2010.2043893
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 22 April 2010
- Issue Date :
- May 2010
- Sponsored by :
- IEEE Solid-State Circuits Society
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