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Design of 2 \times VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology

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2 Author(s)
Chang-Tzu Wang ; Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Ming-Dou Ker

A low-leakage 2× VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the silicon-controlled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD clamp circuit can achieve an ultralow standby leakage current. The new proposed circuit has successfully been verified in a 1-V 65-nm CMOS process, which can achieve 6.5-kV human-body-model and 350-V machine-model ESD levels under ESD stresses, but only consumes a standby leakage current of 0.15 μA at room temperature under normal circuit operating conditions with 1.8-V bias.

Published in:

Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 6 )

Date of Publication:

June 2010

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