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This paper investigates the use of logic implication checkers for the online detection of errors. A logic implication, or invariant relationship, must hold for all valid input conditions; therefore, any violation of this implication will indicate an error due to an intermittent fault. Techniques are presented to efficiently identify the most useful logic implications to include in checker hardware such that the probability of error detection is maximized while minimizing the additional hardware and delay overhead. Results show that significant error detection is possible-even with only a 10% area overhead-while minimizing impact on delay and power.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:29 , Issue: 5 )
Date of Publication: May 2010