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Mechanical stress aware optimization for leakage power reduction

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5 Author(s)
Vivek Joshi ; University of Michigan, Ann Arbor, MI, USA ; Brian Cline ; Dennis Sylvester ; David Blaauw
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Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current complementary metal-oxide-semiconductor technologies. This paper explores how to fully exploit the layout dependence of stress enhancement and proposes a circuit-level, block-based, stress-enhanced optimization algorithm that uses stress-optimized layouts in conjunction with dual-V th assignment to achieve optimal power-performance tradeoffs. We begin by studying how channel stress and drive current depend on layout parameters such as active area length and contact placement, while considering all layout-dependent sources of mechanical stress in a 65 nm industrial process. We then investigate the three main layout properties that impact mechanical stress in this process and discuss how to improve stress-based performance enhancement in standard cell libraries. While varying the stress-altering layout properties of a number of standard cells in a 65 nm industrial library, we show that ?dual-stress? standard cell layouts (analogous to ?dual-V th?) can be designed to achieve drive current differences up to ~ 14% while incurring less than half the leakage penalty of dual-V th. Therefore, when the flexibility of ?dual-stress? assignment is combined with dual-V th assignment (within the proposed joint optimization framework), simulation results for a set of benchmark circuits show that leakage is reduced by ~ 24% on average, for iso-delay, when compared to dual-V th assignment. Since mobility enhancement does not incur the exponential leakage penalty associated with V th assignment, our optimization technique is ideal for leakage power reduction. However, our framework can also be used to achieve higher performance circuits for iso-leakage and our joint optimization framework can be used to reduce delay on average by ~ 5%. In both cases, the proposed - ethod only incurs a small area penalty (<0.5%).

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:29 ,  Issue: 5 )