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As CMOS technology scales down into the deep submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. We propose a combination of a topology and Multi-path routing which can increase fault-Tolerant and Communication load which is suitable for multimedia applications. We compare the performance of Fat-Tree, 2d-Mesh and 3d-Mesh architectures using Multi-path routing in the sense of on chip network design methodology. The simulations of each of the architectures are done with IP and Multi-path routing, two-dimensional and three-dimensional topologies. We also carry out the high level simulation of on chip network using NS-2 to verify the analytical analysis.