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Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.