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A fully digital clock and data recovery (CDR) architecture for multi-link applications is presented. The architecture has independent tolerance to inter-channel skew and timing jitter, and does not rely on data-embedded framing information or a specific equalisation sequence. It is therefore especially suited to low-voltage differential signalling (LVDS) video transceiver applications, and is described in that context. Attained skew tolerance is predicted in theory and successfully compared against silicon prototype measurements.