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Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design

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4 Author(s)
Oh, S. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Jeongha Park ; Wong, S.S. ; Wong, H.-S.P.

A compact model of III-V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22 nm technology III-V SRAM circuit design via III-V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III-V PMOS strength for SRAM to be viable.

Published in:

Quality Electronic Design (ISQED), 2010 11th International Symposium on

Date of Conference:

22-24 March 2010