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A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design

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4 Author(s)
Bingbing Xia ; Dept of Electron. Eng., Tsinghua Univ., Beijing, China ; Fei Qiao ; Huazhong Yang ; Hui Wang

To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional software redundancy (time redundant).Therefore, it will be a good choice for the fault-tolerant architecture for the future high-reliable multi-core systems.

Published in:

Quality Electronic Design (ISQED), 2010 11th International Symposium on

Date of Conference:

22-24 March 2010

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