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A robust and low power dual data rate (DDR) flip-flop using c-elements

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3 Author(s)
Devarapalli, S.V. ; Dept. of ECE, Univ. of New Mexico, Albuquerque, NM, USA ; Zarkesh-Ha, P. ; Suddarth, S.C.

To maintain the performance of digital systems, while reducing the energy consumption, implementation of dual edge flip flops has recently become the focus of many researchers. This paper presents a new robust and low power dual edge flip-flop using c-elements. Unlike the existing dual data rate (DDR) flip flops [1-4], the proposed circuit uses the direct clock pulses to latch the data, without a need for additional pulse generator circuitry for the clock signal, which lowers the clock dynamic power consumption by factor of 2×. Moreover, because of its simplicity with very low transistor count, it provides a more robust solution for DDR flip-flops. In comparison with ep-DSFF (explicit-pulsed static hybrid flop) [1] at 45 nm CMOS process, the proposed DDR-FF consumes 32% less power, with 12% less C2Q delay. The power-delay product of the proposed DDR-FF is 41% better than its counterpart, ep-DSFF. The proposed DDR-FF uses only 24 transistors and can easily be implemented into the cell libraries for high performance and low power ASIC design flow.

Published in:

Quality Electronic Design (ISQED), 2010 11th International Symposium on

Date of Conference:

22-24 March 2010