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Hot carrier effects on CMOS phase-locked loop frequency synthesizers

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2 Author(s)
Yang Liu ; Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA ; Srivastava, A.

Two CMOS phase-locked loop chips are designed and fabricated in 0.5 ¿m n-well CMOS process using single-ended voltage-controlled oscillator and differential voltage-controlled oscillator circuits. Hot carrier effects, jitter and phase noise performances are investigated and analyzed. On-chip measured experimental results show that for the phaselocked loop with the single-ended voltage-controlled oscillator working at 500 MHz carrier frequency, phase noise is -76 dBc/Hz at 10 kHz offset frequency and -119 dBc/Hz at 1 MHz offset frequency. For the phase-locked loop with differential voltage-controlled oscillator working at 500 MHz, phase noise reaches -82 dBc/Hz at 1 kHz offset frequency and -122 dBc/Hz at 1 MHz offset frequency. Tuning frequencies of the two phase-locked loops decrease about 100-200 MHz when subjected to four hours of hot carrier stress. The single-ended VCO gain decreases from 260 MHz to 70 MHz due to hot carrier stress. For the phase-locked loop with the differential voltage-controlled oscillator, a 50 ps RMS jitter increase is observed under hot carrier stress.

Published in:

Quality Electronic Design (ISQED), 2010 11th International Symposium on

Date of Conference:

22-24 March 2010

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