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Investigation of the Tilera processor for real time hazard detection and avoidance on the Altair Lunar Lander

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5 Author(s)
Villalpando, C.Y. ; Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA ; Johnson, A.E. ; Some, R. ; Oberlin, J.
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The High Performance Processor (HPP) Task of the Advanced Avionics and Processor Systems (AAPS) Project, part of the Exploration Technology Development Program (ETDP), was to evaluate several high performance multicore processor architectures with respect to their ability to provide real time hazard detection and avoidance for the Constellation Program's Altair Lunar Lander. In this paper we review the Tilera Tile64 processor, the hazard detection and avoidance algorithm, strategies for parallelizing these algorithms, and preliminary performance study results. We were presented with the requirements of 30 Hz LIDAR frame processing rate and 10 second processing time for ALHAT HDA processing and were able to meet that requirement with the Tile64. We then project the performance of these algorithms on the OPERA MAESTRO Processor, a radiation tolerant version of the Tile 64 being developed by the Boeing Company.

Published in:

Aerospace Conference, 2010 IEEE

Date of Conference:

6-13 March 2010