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The Time to Digital Converter (TDC) concept is quite useful to obtain crucial timing information for nuclear radiation detection such as PET imaging applications. The high resolution nature of TDCs makes them sensitive to process and temperature variations. Thus, a calibration procedure must often be performed to improve measurements. Moreover, field programmable gate array (FPGA)-based TDC exacerbates this problem because the transistor topology is fixed on the fabric for low cost purposes. A Sub-Nanosecond Time Interval Detection System, able to overcome process and temperature (PT) variations, was designed and implemented in an FPGA. Unlike other FPGA-based TDCs, this new solution uses embedded PT invariant digital delay lines and deserializers included in I/O ports, along with a stable clock oscillator resulting in low logic usage. The proposed design consists of oversampling digital signals to enable the creation of absolute timestamps down to 75 ps resolution (31.85 psRMS). As a proof of concept, this paper reports timing resolution down to 321.5 ps.